The present invention relates to a semiconductor memory circuit and, more particularly, to a hold-current controlling circuit mounted therein.
Generally, a semiconductor memory circuit is mainly comprised of a large number of memory cells. The memory cells are arranged at cross points of word lines and bit lines. A desired memory cell is selected by both a word decoder, connected to the word lines, and a bit decoder, connected to the bit lines, at the ends thereof. Data to be read is produced from the other end of the corresponding bit line to which the selected memory cell is connected, after data to be written is supplied to the memory cell.
Each memory cell is usually connected not only to a word line but also to a hold line through which the above mentioned hold current flows. The hold current functions to sustain the data stored in the memory cells. The hold current is absorbed by a hold-current source. It should be noted that the hold-current source absorbs a discharge current, too. The discharge current is created by electric charges held by a parasitic capacitor of the memory cells and also by a stray capacitor distributed along the word line. The more the discharge current is absorbed by the hold-current source, the higher the accessing speed of the memory cells becomes. Accordingly, in order to absorb the discharge current very quickly, a hold-current controlling circuit as described above has been proposed. The hold-current controlling circuit cooperates with the hold-current source and absorbs not only the hold current but also the above-mentioned discharge current created by the electric charges held by the capacitors.
Many types of hold-current controlling circuits have been proposed and put into practical use. However, all of the prior art hold-current controlling circuits have an identical disadvantage in that, although each of these hold-current controlling circuits is effective for achieving a high speed accessing operation with respect to a word line which changes from a selection status to a non-selection status, the hold-current controlling circuits are not effective for achieving a high speed accessing operation with respect to a word line which changes from a non-selection status to a selection status. The term selection status means a condition in which a word line is being selected by a word decoder, while the term non-selection status means a condition in which a word line is not being selected by the word decoder.